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| SP691A/693A/800L/800M SIGNAL PROCESSING EXCELLENCE Low Power Microprocessor Supervisory with Battery Switch-Over FEATURES Precision 4.65V/4.40V Voltage Monitoring 200ms Or Adjustable Reset Time 100ms, 1.6s Or Adjustable Watchdog Time 60A Maximum Operating Supply Current 2.0A Maximum Battery Backup Current 0.1A Maximum Battery Standby Current Power Switching 250mA Output in Vcc Mode (0.6) 25mA Output in Battery Mode (5) On-Board Gating of Chip-Enable Signals Memory Write-Cycle Completion 6ns CE Gate Propagation Delay Voltage Monitor for Power-Fail or Low Battery Backup-Battery Monitor RESET Valid to Vcc=1V 1% Accuracy Guaranteed (SP800L/800M) Pin Compatible Upgrade to MAX691A/693A/ 800L/800M VBATT VOUT Vcc GND BATT ON LOWLINE OSCIN OSCSEL 1 2 3 4 Corporation TOP VIEW 16 RESET 15 RESET 14 WDO 13 CEIN 12 CEOUT 11 WDI 10 9 5 6 7 8 PFO PFI DIP/SO Now Available in Lead Free Packaging DESCRIPTION The SP691A/693A/800L/800M is a microprocessor (P) supervisory circuit that integrates a myriad of components involved in discrete solutions to monitor power-supply and battery-control functions in P and digital systems. The SP691A/693A/800L/800M offers complete P monitoring and watchdog functions. The SP691A/693A/800L/800M is ideal for a low-cost battery management solution and is well suited for portable, battery-powered applications with its supply current of 35A. The 6ns chip-enable propagation delay, the 25mA current output in battery-backup mode, and the 250mA current output in standard operation also makes the SP691A/693A/800L/800M suitable for larger scale, high-performance equipment. Part Number SP691A SP693A SP800L SP800M RESET Threshold 4.65V 4.40V 4.65V 4.40V RESET Accuracy +125mV +125mV +50mV +50mV PFI Accuracy +4% +4% +1% +1% Backup-Battery Switch YES YES YES YES Date: 5/25/04 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over (c) Copyright 2004 Sipex Corporation 1 These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Terminal Voltages (with respect to GND) VCC.......................................................................................-0.3V to +6V VBATT.....................................................................................-0.3V to +6V All Other Inputs........................................................-0.3V to (VCC +0.3V) Input Currents VCC Peak...........................................................................................1.0A VCC Continuous.............................................................................250mA VBATT Peak....................................................................................250mA VBATT Continuous............................................................................25mA GND, BATT ON............................................................................100mA All Other Inputs..............................................................................25mA ABSOLUTE MAXIMUM RATINGS Enhanced ESD Specifications........................+4kV Human Body Model Power Dissipation Per Package 16-pin PDIP (derate 14.3mW/OC above +70OC).......................1150mW 16-pin Narrow SOIC (derate 13.6mW/OC above 70OC)............1090mW 16-pin Wide SOIC (derate 11.2mW/OC above 70OC).................900mW Storage Temperature....................................................-65OC to +150OC Lead Temperature (soldering,10 sec).........................................+300OC ELECTRICAL CHARACTERISTICS VCC = +4.75V to +5.5V for the SP691A/800L, VCC = +4.5V to +5.5V for the SP693A/800M, VBATT = +2.8V, and TAMB = TMIN to TMAX unless otherwise noted. Typical values apply at TAMB=+25OC. PARAMETERS Operating Voltage Range, VCC or VBATT, NOTE 1 Output Voltage, VOUT in Normal Operating Mode MIN. 0 VCC-0.05 VCC-0.3 VCC-0.2 TYP. MAX. 5.5 UNITS CONDITIONS V VCC=4.5V, IOUT=25mA VCC=4.5V, IOUT=250mA VCC=3.0V, VBATT=2.8V, IOUT=100mA VCC=4.5V VCC=3.0V VBATT=4.5V, IOUT=20mA VBATT=2.8V, IOUT=10mA VBATT=2.0V, IOUT=5mA VBATT=4.5V VBATT=2.8V VBATT=2.0V VCC>(VBATT-1V), excluding IOUT VCC<(VBATT-1.2V), VBATT=2.8V, excluding IOUT VCC>(VBATT+0.2V), excluding IOUT power-up power-down Peak to Peak VCC-0.015 VCC-0.15 VCC-0.09 0.6 0.9 1.2 2.0 V VCC-to-VOUT On-Resistance VOUT in Battery-Backup Mode VBATT-0.3 VBATT-0.25 VBATT-0.15 VBATT-0.1 VBATT-0.07 VBATT-0.05 5 7 10 35 15 25 30 60 V VBATT-to-VOUT On-Resistance Supply Current in Normal Operating Mode, IVcc Supply Current in BatteryBackup Mode, IBATT, NOTE 2 VBATT Standby Current, IBATT, NOTE 3 Battery Switchover Threshold -0.1 A A A 0.001 2.0 0.02 VBATT+0.03 VBATT-0.03 60 V mV Battery Switchover Hysteresis Date: 5/25/04 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over (c) Copyright 2004 Sipex Corporation 2 VCC = +4.75V to +5.5V for the SP691A/800L, VCC = +4.5V to +5.5V for the SP693A/800M, VBATT = +2.8V, and TAMB = TMIN to TMAX unless otherwise noted. Typical values apply at TAMB=+25OC. ELECTRICAL CHARACTERISTICS PARAMETERS BATT ON Output Low Voltage BATT ON Output Short Circuit Current MIN. TYP. 0.1 0.7 60 MAX. 0.4 1.5 100 UNITS CONDITIONS V mA A ISINK=3.2mA ISINK=25mA sink current source current 1 15 RESET, LOWLINE, AND WATCHDOG TIMER Reset Threshold Voltage 4.50 4.25 4.60 4.35 4.65 4.40 4.65 4.40 15 80 800 140 200 280 4.75 4.50 4.70 4.45 SP691A SP693A SP800L SP800M center-to-peak power down power down power-up V Reset Threshold Hysteresis VCC to RESET Delay LOWLINE to RESET Delay Reset Active Timeout Period for the Internal Oscillator Reset Active Timeout Period for the External Clock, NOTE 4 Watchdog Timeout Period for the Internal Oscillator Watchdog Timeout Period for the External Clock, NOTE 4 Minimum Watchdog Input Pulse Width RESET Output Voltage 3.5 RESET Output Short-Circuit Current RESET Output Voltage Low, NOTE 5 LOWLINE Output Voltage 3.5 LOWLINE Output Short Circuit Current WDO Output Voltage 3.5 WDO Output Short-Circuit Current Date: 5/25/04 mV s ns ms 2048 1.0 70 1.6 100 4096 1024 100 0.004 0.1 0.3 0.4 2.25 140 clock power-up cycles sec ms long period short period clock long period cycles short period ns VIL=0.8V,VIH=0.75xVCC ISINK=50A, VCC=1V, VCC falling ISINK=3.2mA, VCC=4.25V ISOURCE=1.6mA, VCC=5V output source current ISINK=3.2mA ISINK=3.2mA, VCC=4.25V ISOURCE=1A, VCC=5V output source current ISINK=3.2mA ISOURCE=500A, VCC=5V output source current V 7 0.1 0.1 20 0.4 0.4 mA V V A V mA 15 0.1 100 0.4 3 10 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over (c) Copyright 2004 Sipex Corporation 3 ELECTRICAL CHARACTERISTICS VCC = +4.75V to +5.5V for the SP691A/800L, VCC = +4.5V to +5.5V for the SP693A/800M, VBATT = +2.8V, and TAMB = TMIN to TMAX unless otherwise noted. Typical values apply at TAMB=+25OC. PARAMETERS WDI Threshold Voltage, NOTE 6 WDI Input Current MIN. 0.75xVCC TYP. MAX. UNITS V A CONDITIONS VIH VIL WDI=0V WDI=VOUT 0.8 -50 -10 20 50 POWER-FAIL COMPARATOR PFI Input Threshold 1.237 1.200 1.225 PFI Leakage Current PFO Output Voltage 3.5 PFO Short Circuit Current 1 PFI-to-PFO Delay 1.25 1.25 +0.01 0.1 1.263 1.300 1.275 +25 0.4 V nA V mA A s SP691A/693A, VCC=5V SP800L/800M, VCC=5V ISINK=3.2mA ISOURCE=1A, VCC=5V output sink current output source current VOD=15mV VOD=15mV 60 15 25 60 100 CHIP-ENABLE GATING CEIN Leakage Current CEIN to CEOUT Resistance, NOTE 7 CEOUT Short-Circuit Current (RESET Active) CEIN to CEOUT Propagation Delay, NOTE 8 CEOUT Output Voltage High (RESET Active) RESET to CEOUT Delay INTERNAL OSCILLATOR OSCIN Leakage Current OSCIN Input Pull-Up Current OSCSEL Input Pull-Up Current OSCIN Frequency Range OSCIN External Oscillator Threshold Voltage OSCIN Frequency with External Capacitor VOUT-0.3 0.10 10 10 200 VOUT-0.6 3.65 2 2.0 +5.0 100 100 A A A kHz V OSCSEL=0V OSCSEL=VOUT or floating, OSCIN=0V OSCSEL=0V OSCSEL=0V VIH VIL OSCSEL=0V, COSC=47pF 3.5 2.7 12 0.1 +0.005 65 +1 150 A mA disable mode enable mode 0.75 2.0 disable mode, CEOUT=0V 50 source impedance driver, CLOAD=50pF VCC=5V, IOUT= 100A VCC=0V, VBATT=2.8V, IOUT=1A power-down 6 10 ns V s kHz Date: 5/25/04 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over (c) Copyright 2004 Sipex Corporation 4 ELECTRICAL CHARACTERISTICS VCC = +4.75V to +5.5V for the SP691A/800L, VCC = +4.5V to +5.5V for the SP693A/800M, VBATT = +2.8V, and TAMB = TMIN to TMAX unless otherwise noted. Typical values apply at TAMB=+25OC. NOTE 1: Either VCC or VBATT can go to 0V, if the other is greater than 2.0V. NOTE 2: The supply current drawn by the SP691A/693A/800L/800M from the battery (excluding IOUT) typically goes to 5A when (VBATT - 1V) < VCC < VBATT. In most applications, this is a brief period as VCC falls through this region. NOTE 3: "+" = battery-discharging current, "-" = battery-charging current. NOTE 4: Although presented as typical values, the number of clock cycles for the reset and watchdog timeout periods are fixed and do not vary with process or temperature. NOTE 5: RESET is an open-drain output and sinks current only. NOTE 6: WDI is internally connected to a voltage divider between VOUT and GND. If unconnected, WDI is driven to 1.6V (typ), disabling the watchdog function. NOTE 7: The chip-enable resistance is tested with VCC = +4.75V for the SP691A/800L and VCC = +4.5V for the SP693A/800M. CEIN = CEOUT = VCC/2. NOTE 8: The chip-enable propagation delay is measured from the 50% point at CEIN to the 50% point at CEOUT. TYPICAL PERFORMANCE CHARACTERISTICS (TAMB = 25 C, unless otherwise noted) o 2.5 43 40 VCC = 5V VBATT = 2.8V 2.0 VCC = 1.6V VBATT = 2.8V VBATT Current (A) -30 0 30 60 90 Temperature (oC) 120 VCC Current (A) 1.5 1.0 0.5 0.0 -0.5 -60 -30 0 30 60 90 Temperature (oC) 120 150 37 34 31 28 25 -60 Figure 1. VCC Supply Current vs. Temperature (Normal Operating Mode) Figure 2. Battery Supply Current vs. Temperature (Battery-Backup Mode) 75.0 14 VCC = 4.75V VBATT = 2.8V CE IN = VCC/2 12 10 VCC = 0V CE-IN Resistance () 70.0 65.0 60.0 55.0 50.0 45.0 Resistance () 8 6 4 2 0 VBATT = 2V VBATT = 2.8V VBATT = 4.5V -60 -30 0 30 60 90 Temperature (oC) 120 150 40.0 -80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (oC) Figure 3. Chip-Enable On-Resistance vs. Temperature Date: 5/25/04 Figure 4. VBATT to VOUT On-Resistance vs. Temperature SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over (c) Copyright 2004 Sipex Corporation 5 TYPICAL PERFORMANCE CHARACTERISTICS 1.256 0.9 VCC = 4.5V VBATT = 2.8V 1.252 VCC = 5V VBATT = 0V PFI Threshold (V) -30 0 30 60 90 Temperature (oC) 120 150 Resistance () 0.7 1.248 1.244 1.240 1.236 -60 -30 0 30 60 90 Temperature (oC) 120 150 0.5 0.3 -60 Figure 5. VCC to VOUT On-Resistance vs. Temperature Figure 6. PFI Threshold vs. Temperature 4.69 4.68 VBATT = 0V 400 350 300 VCC Rising VCC Falling Sourcing VCC = 5V Sinking VCC = 4.25V Reset Threshold (V) 4.67 Resistance () 150 4.66 4.65 4.64 4.63 4.62 4.61 4.60 -60 -30 0 250 200 150 100 50 30 60 90 Temperature (oC) 120 0 -60 -30 0 30 60 90 Temperature (oC) 120 150 Figure 7. Reset Threshold vs. Temperature Figure 8. RESET Output Resistance vs. Temperature 0.240 1.E-04 Reset Timeout Period (s) 0.230 0.220 0.210 0.200 0.190 0.180 -60 VBATT Current (A), Log Scale VCC = 5V VBATT = 2.8V 1.E-05 1.E-06 1.E-07 1.E-08 1.E-09 1.E-10 1.E-11 1.E-12 1.E-13 1.E-14 0 1 2 VCC (V) 3 4 5 VBATT = 2.8V -30 0 30 60 90 Temperature (oC) 120 150 Figure 9. Reset Delay vs. Temperature Date: 5/25/04 Figure 10. Battery Current vs. Input Supply Voltage SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over (c) Copyright 2004 Sipex Corporation 6 TYPICAL PERFORMANCE CHARACTERISTICS 1000 100 Propagation Delay (s) Watchdog and Reset Timeout Period (s) Long Watchdog Timeout Period Reset Active Timeout Period Short Watchdog Timeout Period 30 25 20 15 10 5 0 VCC = 5V VBATT = 2.8V 50 driver 10 1 VCC = 5V VBATT = 2.8V 0.1 10 100 1000 OSCIN Capacitor (pF) 10000 0 50 100 150 200 Cload (pF) 250 300 350 Figure 11. Watchdog and Reset Timeout Period vs. OSCIN Timing Capacitor (COSC) Figure 12. Chip-Enable Propagation Delay vs. CEOUT Load Capacitance 1000 1000 Voltage Drop (mV) Voltage Drop (mV) 100 100 10 VCC = 4.5V VBATT = 0V Slope = 0.6 10 VCC = 4.5V VBATT = 0V Slope = 5 1 1 10 IOUT (mA) 100 1000 1 1 10 IOUT (mA) 100 1000 Figure 13. VCC to VOUT vs. Output Current (Normal Operating Mode) Figure 14. VBATT to VOUT vs. Output Current (BatteryBackup Mode) VCC Reset Threshold RESET LOWLINE +5V 0V 80s HI LOW 1.1s HI LOW 16s HI CEOUT LOW Figure 15. VCC to LOWLINE and CEOUT Delay Date: 5/25/04 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over (c) Copyright 2004 Sipex Corporation 7 PINOUT TOP VIEW VBATT VOUT Vcc GND BATT ON LOWLINE OSCIN OSCSEL 1 2 3 4 Corporation 16 RESET 15 RESET 14 WDO 13 CEIN 12 CEOUT 11 WDI 10 9 5 6 7 8 PFO PFI Pin 7 -- OSCIN -- External Oscillator Input. When OSCSEL is unconnected or driven HIGH, a 10A pull-up connects from VOUT to this input pin, the internal oscillator sets the reset and watchdog timeout periods, and this input pin selects between fast and slow watchdog timeout periods. When OSCSEL is driven LOW, the reset and watchdog timeout periods may be set either by a capacitor from this input pin to ground or by an external clock at this pin (refer to Figure 21). Pin 8 -- OSCSEL -- Oscillator Select. When OSCSEL is unconnected or driven HIGH, the internal oscillator sets the reset delay and watchdog timeout period. When OSCSEL is driven LOW, the external oscillator input pin, OSCIN, is enabled (refer to Table 1). This input pin has a 10A internal pull-up. Pin 9 -- PFI -- Power-Fail Input. This is the noninverting input to the power-fail comparator. When PFI is less than 1.25V, PFO goes low. Connect PFI to GND or VOUT when not used. Pin 10 -- PFO -- Power-Fail Output. This is the output of the power-fail comparator. PFO goes low when PFI is less than 1.25V. This is an uncommitted comparator, and has no effect on any other internal circuitry. Pin 11 -- WDI -- Watchdog Input. This is a three-level input pin. If WDI remains either HIGH or LOW for longer than the watchdog timeout period, WDO goes LOW and RESET is asserted for the reset timeout period. WDO remains LOW until the next transition at this input pin. Leaving this input pin unconnected disables the watchdog function. This input pin connects to an internal voltage divider between VOUT and ground, which sets it to mid-supply when left unconnected. DIP/SO PIN ASSIGNMENTS Pin 1 -- VBATT -- Battery-Backup Input. Connect to the external battery supply or supercharging capacitor and charging circuit. If a backup battery is not provided, connect this pin to ground. Pin 2 --VOUT -- Output Supply Voltage. VOUT connects to VCC when VCC is greater than VBATT and VCC is above the reset threshold. When VCC falls below VBATT and V CC is below the reset threshold, VOUT connects to VBATT. Connect a 0.1F capacitor from VOUT to GND. Pin 3 -- VCC -- +5V Input Supply Voltage. Pin 4 -- GND -- Ground reference for all signals. Pin 5 -- BATT ON -- Battery On Output. Goes high when VOUT switches to VBATT. Goes low when VOUT switches to VCC. Connect the base of a PNP through a current-limiting resistor to BATT ON for VOUT current requirements greater than 250mA. Pin 6 -- LOWLINE -- Low Line Output. This output pin goes LOW when VCC falls below the reset threshold voltage. This output pin returns to it's HIGH output as soon as VCC rises above the reset threshold voltage. Date: 5/25/04 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over (c) Copyright 2004 Sipex Corporation 8 Pin 12 -- CEOUT -- Chip-Enable Output. This output pin goes LOW only when CEIN is LOW and VCC is above the reset threshold voltage. If CEIN is LOW when RESET is asserted, this output pin will stay low for 16s or until CEIN goes HIGH, whichever occurs first. Pin 13 -- CEIN -- Chip-Enable Input. This is the input pin to the chip-enable gating circuit. If this input pin is not used, connect it to ground or VOUT. Pin 14 -- WDO -- Watchdog Output. If WDI remains HIGH or LOW longer than the watchdog timeout period, this output pin goes LOW and RESET is asserted for the reset timeout period. This output pin returns HIGH on the next transition at WDI. This output pin remains HIGH if WDI is unconnected. Pin 15 -- RESET -- Active LOW Reset Output. This output pin goes LOW whenever VCC falls below the reset threshold. This output pin will remain low typically for 200ms after VCC crosses the reset threshold voltage on power-up. Pin 16 -- RESET -- Active HIGH Reset Output. This output pin is open drain and the inverse of RESET. PFI 9 10 PFO WDI 11 Watchdog Transition Detector 1.25V Watchdog Timer 14 15 Reset Generator CEOUT Control 6 16 WDO RESET RESET OSCSEL OSCIN 8 7 Reset / Watchdog Timebase 4.65V or 4.40V* LOWLINE VCC 3 2 VOUT 5 BATT ON VBATT CEIN 1 13 * 4.65V for the SP691A/800L 4.40V for the SP693A/800M 4 GND 12 CEOUT Figure 16. Internal Block Diagram of the SP691A/693A/800L/800M Date: 5/25/04 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over (c) Copyright 2004 Sipex Corporation 9 Unregulated DC R1 Regulated +5V R2 VCC VCC P RESET NMI A0-A15 I/O LINE Backup Supply BUS PFI RESET PFO WDI VBATT WDO alarm system status indicator LOWLINE Address Decode BATT ON CEIN CMOS RAM1 to RAMn VCC VOUT CEOUT 0.1F GND Figure 17. Typical Application Circuit of the SP691A/693A/800L/800M FEATURES The SP691A/693A/800L/800M devices are microprocessor (P) supervisory circuits that monitor the power supplied to digital circuits such as microprocessors, microcontrollers, or memory. The SP691A/693A/800L/800M series is an ideal solution for portable, batterypowered equipment that require power supply monitoring. The SP691A/693A/800L/800M watchdog functions will continuously oversee the operational status of a system. Implementing the SP691A/693A/800L/800M series will reduce the number of components and overall complexity in a design that requires power supply monitoring circuitry. The operational features and benefits of this series are described in more detail below. Date: 5/25/04 THEORY OF OPERATION The SP691A/693A/800L/800M series is a complete P supervisor IC and provides the following main functions: 1) P reset Reset output is asserted during power fluxiations such as power-up, power-down, and brown out conditions, and is guaranteed to be in the correct state for VCC down to 1V, even with no battery in the circuit. 2) P reset Reset output is pulsed if the optional watchdog timer has not been toggled within a specified time. 3) Power Fail Comparator Provides for power-fail warning and low-battery detection, or monitors another power supply. 10 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over (c) Copyright 2004 Sipex Corporation 4) Watchdog function Monitors P activity where the watchdog output goes to a logic LOW state if the watchdog input is not toggled for greater than the timeout period. 5) Internal switch Switches over from VCC to VBATT if the VCC falls below the reset threshold. RESET and RESET Outputs The SP691A/693A/800L/800M devices' RESET and RESET outputs ensure that the P powers up in a known state, and prevents code-execution errors during power-down or brownout conditions. The RESET output is active low, and typically sinks 3.2mA at 0.1V saturation voltage in its active state. When deasserted, RESET sources 1.6mA at typically VOUT - 0.5V. RESET output is open drain, active high, and typically sinks 3.2mA with a saturation voltage of 0.1V. When no backup battery is used, RESET output is guaranteed to be valid down to VCC = 1V, and an external 10k pull-down resistor on RESET ensures that RESET will be valid with VCC down to GND as shown on Figure 18. As VCC goes below 1V, the gate drive to the RESET output switch reduces accordingly, increasing the RDS(ON) and the saturation voltage. The 10k pull-down resistor ensures the parallel combination of switch plus resistor is around RESET 15 10k TO P RESET Corporation Figure 18. External Pull-down Resistor Ensures RESET is Valid with VCC Down to Ground. 10k and the output saturation voltage is below 0.4V while sinking 40A. When using a 10k external pull-down resistor, the high state for the RESET output with Vcc = 4.75V is 4.5V typical. For battery voltages less than or equal to 2V connected to VBATT, RESET and RESET remains valid for VCC from 0V to 5.5V. RESET and RESET are asserted when VCC falls below the reset threshold and remain asserted for the Reset Timeout Period (200ms nominal) after VCC rises above the reset threshold voltage on power-up. Refer to Figure 19. The devices' battery-switchover comparator does not affect reset assertion. However, both reset outputs are asserted in battery-backup mode since VCC must be below the reset threshold to enter this mode. Vcc RESET THRESHOLD CE IN CE OUT 12 100s 100s RESET RESET Figure 19. Reset and Chip-Enable Timing Date: 5/25/04 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over (c) Copyright 2004 Sipex Corporation 11 WDI WDO t2 RESET t1 t1 t3 t1 = RESET Timeout Period t2 = Normal Watchdog Timeout Period t3 = Watchdog Timeout Period Immediately After RESET Figure 20. Watchdog Timeout Period and Reset Active Time Watchdog Function The watchdog monitors P activity via the Watchdog Input (WDI). If the P becomes inactive, RESET and RESET are asserted. To use the watchdog function, connect WDI to a bus line or P I/O line. If WDI remains high or low for longer than the watchdog timeout period (1.6s nominal). WDO, RESET, and RESET are asserted, indicating a software fault or idle conditions. Refer to RESET and RESET Outputs and Watchdog Output sections. Watchdog Input A change of logic state (minimum 100ns duration) at WDI during the watchdog period will reset the watchdog timer. The watchdog default timout is 1.6sec. To disable the watchdog function, leave WDI floating. An internal resistor network (100k equivalent impedance at WDI) biases WDI to approximately 1.6V. Internal comparators detect this level and disable the watchdog timer. When Vcc is below the reset threshold, the watchdog function is disabled and WDI is disconnected from its internal resistor network, thus becoming high impedance. Watchdog Output WDO remains high if there is activity (transition or pulse) at WDI during the watchdog-timeout period. The watchdog function is disabled and WDO is a logic high when VCC is less than the reset threshold or when WDI is an open circuit. In watchdog mode, if no transition occurs at WDI during the watchdog-timeout period, Date: 5/25/04 7 OSCIN X No Connect X No Connect 8 OSCSEL 1.6sec Normal Watchdog Timeout Internal Oscillator 7 OSCIN 8 OSCSEL X No Connect 100ms Normal Watchdog Timeout Internal Oscillator CIN 7 OSCIN 8 OSCSEL Normal Watchdog Timeout = 600 x CIN [ms] 47pF External Oscillator 7 OSCIN 8 OSCSEL Normal Watchdog Timeout = 1024 Clock Periods External Clock Figure 21. Selecting Timeout Periods SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over (c) Copyright 2004 Sipex Corporation 12 Watchdog Timeout Period OSCSEL LOW LOW Floating Floating OSCIN Normal External Clock Input External Capacitor LOW Floating 1024 clocks (600/47pF x C) ms 100 ms 1.6 s Immediately After Reset 4096 clocks (2.4/4.7pf x C) sec 1.6 s 1.6 s 2048 clocks (1200/47pF x C) ms 200 ms 200 ms Reset Timeout Period Table 1. Reset Pulse Width and Watchdog Timeout Selections RESET and RESET are asserted for the reset timeout period (200ms nominal). WDO goes to logic low and remains low until the next transition at WDI. Refer to Figure 20. If WDI is held high or low indefinitely, RESET and RESET will generate 200ms pulses every 1.6s. WDO has a 2 x TTL output characteristic. Selecting an Alternative Watchdog Timeout Period The OSC SEL and OSC IN inputs control the watchdog are reset timeout periods. Floating OSCSEL and OSCIN or tying them both to VOUT selects the nominal 1.6s watchdog timeout period and 200ms reset timout period. Connecting OSCIN to ground and floating or connecting OSCSEL to VOUT selects a 100ms normal watchdog timeout period and a 1.6s timeout period immediately after reset. The reset timeout period remains 200ms. Refer to Figure 20. Select alternative timeout periods by connecting OSCSEL to ground and connecting a capacitor between OSCIN and ground, or by externally driving OSCIN . A synopsis of this control can be found in Figure 21 and Table 1. Chip-Enable Signal Gating The SP691A/693A/800L/800M devices provide internal gating of chip-enable (CE) signals, to prevent erroneous data from corrupting the CMOS RAM in the event of a power failure. During normal operation, the CE gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The SP691A/ 693A/800L/800M devices use a series transmission gate from CEIN to CEOUT. Refer to Figure 16. Date: 5/25/04 The 10ns maximum CE propagation from CEIN to CE OUT enables the SP691A/693A/800L/ 800M devices to be used with most Ps. Chip-Enable Input CEIN is in high impedance (disabled mode) while RESET and/or RESET are asserted. During a power-down sequence where VCC falls below the reset threshold, CEIN assumes a high impedance state when the voltage at CEIN goes high or 12s after RESET is asserted, whichever occurs first. Refer to Figure 19. During a power-up sequence, CEIN remains high impedance until RESET is deasserted. In the high-impedance mode, the leakage currents into CEIN are <1A over temperature. In the low-impedance mode, the impedance of CEIN appears as a 65 resistor in series with the load at CEOUT. The propagation delay through the CE transmission gate depends on both the source impedance of the drive to CE IN and the capacitive loading on CE OUT (see the Chip-Enable Propagation Delay vs. CE OUT Load Capacitance graph in the Typical Performance Characteristics section). The CE propagation delay is defined from the 50% point on CEIN to the 50% point on CEOUT using a 50 driver and 50pF of load capacitance as in Figure 22. For minimum propagation delay, minimize the capacitive load at CEOUT and use a low output-impedance driver. SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over (c) Copyright 2004 Sipex Corporation 13 +5V VCC VBATT 1 13 CEIN VBATT R1 2.8V 12 4 GND CEOUT CLOAD +2.0V to +5.5V PFI R2 GND PFO LOW BATT Figure 22. Chip Enable Propagation Delay Test Circuit Figure 23. Low-Battery Indicator Circuit Chip-Enable Output In the enabled mode, the impedance of CEOUT is equivalent to 65 in series with the source driving CEIN. In the disabled mode, the 65 transmission gate is off and CEOUT is actively pulled to VOUT. This source turns off when the transmission gate is enabled. LOWLINE Output LOWLINE is the buffered output pin of the reset threshold comparator. Refer to Figure 16. LOWLINE typically sinks 3.2mA at 0.1V. For normal operation where VCC is above the reset threshold, LOWLINE is pulled to VOUT. Power-Fail Comparator The power-fail comparator is an uncommitted comparator that has no effect on the other functions of the SP691A/693A/800L/800M devices. Common uses include low battery detection, as found in Figure 23, and early power-fail detection when the unregulated power is easily accessible as shown in Figure 17. Power-Fail Input The Power-Fail Input (PFI) has a guaranteed input leakage of +25nA max over temperature. The typical comparator delay is 25s from VIL to VOL (power failing), and 60s from VIH to VOH (power being restored). Connect this input to ground if PFI is not used. Date: 5/25/04 Power-Fail Output The Power-Fail Output (PFO) goes low when PFI goes below 1.25V. It sinks 3.2mA with a saturation voltage of 0.1V. With PFI above 1.25V, PFO is actively pulled to VOUT. PFO can be used to generate an NMI for the P, as shown in Figure 17. Battery-Backup Mode The SP691A/693A/800L/800M requires two conditions to switch to battery-backup mode: 1) VCC must be below the reset threshold; 2) VCC must be below VBATT. Table 2 lists the status of the inputs and outputs in batterybackup mode. Battery-On Output The Battery On Output (BATT ON) indicates the status of the internal VCC/battery-switchover comparator, which controls the internal VCC and VBATT switches. For VCC greater that VBATT (ignoring the small hysteresis effect), BATT ON is a logic low. For VCC less than VBATT, BATT ON is a logic high. Use BATT ON to indicate battery-switchover status or to supply base drive to an external pass transistor for higher-current applications. Refer to Figure 17. SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over (c) Copyright 2004 Sipex Corporation 14 NAME VBATT VOUT VCC GND BATT ON LOWLINE OSCIN OSCSEL PFI PF O WDI CEOUT CEIN WDO RESET RESET STATUS Supply current is 1A maximum when VCC<(VBATT-1.2V). VOUT connected to VBATT through an internal PMOS switch. Battery switchover comparator monitors VCC for active switchover. VCC is disconnected from VOUT. 0V reference for all signals. Logic HIGH. The open-circuit output voltage is equal to VOUT. Logic LOW. OSCIN is ignored and is at high-Z. OSCSEL is ignored and is at high-Z. The power-fail comparator is disabled. The power-fail comparator is disabled. PFO is forced to logic LOW. WDI is ignored and is at high-Z. Logic HIGH. The open-circuit output voltage is equal to VOUT. High-Z. Logic HIGH. The open-circuit output voltage is equal to VOUT. Logic LOW. High-Z. PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Table 2. Input and Output Status in Battery-Backup Mode; to enter the Battery-Backup Mode, VCC must be less than the reset threshold and less than VBATT. VBATT VCC SW1 D1 D2 SW2 VOUT 0.1F Input Supply Voltage The Input Supply Voltage (VCC) should be a regulated +5V source. VCC connects to VOUT via a parallel diode and a large PMOS switch. The switch carries the entire current load for currents less than 250mA. The parallel diode carries any current in excess of 250mA. Both the switch and the diode have impedances less than 1 each. Refer to Figure 24. The maximum continuous current is 250mA, but power-on transients may reach a maximum of 1A. Backup-Battery Input The Backup-Battery Input (VBATT) is similar to VCC, except the PMOS switch and parallel diode are much smaller. Refer to Figure 24. Accordingly, the on-resistances of the diode and the switch are each approximately 10. Figure 24. VCC and VBATT to VOUT Switch Date: 5/25/04 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over (c) Copyright 2004 Sipex Corporation 15 +5V 3 Vcc 1 0.47F 2 1N4148 2) Battery-backup mode where VCC is typically within 0.7V below VBATT. All circuitry is powered from V BATT and the supply current from the battery is typically less than 5A. VOUT VBATT 3) Battery-backup mode where VCC is less than V BATT by at least 0.7V. V BATT supply current is less than 1A max. Using High Capacity Capacitor with the SP691A/693A/800L/800M Series VBATT has the same operating voltage range as VCC, and the battery-switchover threshold voltages are typically +30mV centered at VBATT, allowing use of a capacitor and a simple charging circuit as a backup source. Refer to Figure 25. If VCC is above the reset threshold and VBATT is 0.5V above VCC, current flows to VOUT and VCC from VBATT until the voltage at VBATT is less than 0.5V above VCC. Leakage current through the capacitor charging diode and SP691A/693A/800L/800M internal power diode eventually discharges the capacitor to VCC. Also, if VCC and VBATT start from 0.5V above the reset threshold and power is lost at VCC, the capacitor on VBATT discharges through VCC until VBATT reaches the reset threshold; the SP691A/693A/800L/800M devices then switch to battery-backup mode. Using Separate Power Supplies for VBATT and VCC If using separate power supplies for VCC and VBATT, VBATT must be less than 0.3V above VCC when VCC is above the reset threshold. As described in the previous section, if VBATT exceeds this limit and power is lost at VCC, current flows continuously from VBATT to VCC via the VBATT-to-VOUT diode and the VOUT-to-VCC switch until the circuit is broken. Refer to Figure 24. Alternative Chip-Enable Gating Using memory devices with CE and CE inputs allows the CE loop of the SP691A/693A/800L/ 800M series to be bypassed. To do this, connect CEIN to ground, pull up CEOUT to VOUT, Figure 25. High Capacity Capacitor on VBATT Continuous current should be limited to 25mA and peak currents (only during power-up) limited to 250mA. The reverse leakage of this input is less than 1A over temperature and supply voltage. Output Supply Voltage The Output Supply Voltage (VOUT) supplies all the current to the external system and internal circuitry. All open-circuit outputs will assume the VOUT voltage in their high states rather than the VCC voltage. At the maximum source current of 250mA, VOUT will typically be 150mV below VCC. VOUT should be decoupled with 0.1F capacitor. TYPICAL APPLICATIONS The SP691A/693A/800L/800M devices are not short-circuit protected. Shorting VOUT to ground, other than power-up transients such as charging a decoupling capacitor, may destroy the device. All open-circuit outputs swing between VOUT and GND rather than VCC and GND. If long leads connect to the chip inputs, ensure that these lines are free from ringing and other conditions that would forward bias the chip's protection diodes. There are three distinct modes of operation: 1) Normal operating mode with all circuitry powered from VCC. Typical supply current from VCC is 35A, while only leakage currents flow from the battery. Date: 5/25/04 ( Corporation GND 4 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over (c) Copyright 2004 Sipex Corporation 16 +5V VIN *Minimum value of RP is 1k. Maximum value of RP is dependent on the connected number of RAMs, n. CEIN 13 2 VOUT RP* GND 4 12 CEOUT CE CE RAM1 VCC PFI R3 PFO *C1 R1 R2 *optional GND RAM2 connect to P VTRIP = 1.25 R2 R1 + R2 CE CE Active-HIGH CE Logic Lines for Memory Devices CE RAM3 CE PFO 1.25 R2 = VL - 1.25 5.0 - 1.25 + R3 R1 1.25 R2 || R3 R1 + R2 || R3 VH = CE RAMn CE +5V 0V 0V VL VTRIP VH VIN Figure 26. Alternate Chip Enable Gating Figure 27. Adding Hysteresis to the Power-Fail Comparator and connect CEOUT to the CE input of each memory device as shown in Figure 26. The CE input of each part then connects directly to the chip-select logic, which does not have to gated by the SP691A/693A/800L/800M devices. Adding Hysteresis to the Power-Fail Comparator Hysteresis adds noise margin to the power-fail comparator and prevents repeated triggering of PFO when VIN is near the power-fail comparator trip point. Figure 27 shows how to add hysteresis to the power-fail comparator. Select the ratio of R1 and R2 such that PFI sees 1.25V when VIN falls to the desired trip point (VTRIP). Resistor R3 adds hysteresis. It will typically be an order of magnitude greater than R1 or R2. The current through R1 and R2 should be at least 1A to ensure that the 25nA (max) PFI input current does not shift the trip point. R3 should be larger than 10k to prevent it from loading down the PFO pin. Capacitor C1 adds additional noise rejection. Monitoring a Negative Voltage The power-fail comparator can be used to monitor a negative supply voltage using the circuit shown in Figure 28. When the negative supply is valid, PFO is low. When the negative supply voltage drops, PFO goes high. This circuit's accuracy is affected by the PFI threshold tolerance, the VCC voltage, and resistors R1 and R2. Backup-Battery Replacement The backup battery may be disconnected while VCC is above the reset threshold. No precautions are necessary to avoid spurious reset pulses. Date: 5/25/04 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over (c) Copyright 2004 Sipex Corporation 17 +5V VCC PFI R2 PFO VGND 5.0 - 1.25 = 1.25 - VTRIP R2 R1 PFO +5V 0V *VTRIP 0V R1 160 0.1F Capacitor VOUT to GND Maximum Transient Duration (s) 120 80 Above Line Reset Generated 40 0 1 10 1000 10000 Reset Comparator Overdrive (Reset Threshold Voltage - VCC), (mV) Figure 29. Maximum Transient Duration Without Causing a Reset Pulse vs. Reset Comparator Overdrive V- *VTRIP is a negative voltage Figure 28. Monitoring a Negative Voltage As the amplitude of the transient increases (i.e., goes farther below the reset threshold), the maximum allowable pulse width decreases. Typically, a VCC transient that goes 100mV below the reset threshold and lasts for 40s or less will not cause a reset pulse to be issued. A 100nF bypass capacitor mounted close to the VCC pin provides additional transient immunity. Connecting a Timing Capacitor to OSCIN When OSCSEL is connected to ground, OSCIN disconnects from its internal 10A pull-up and is internally connected to a +100nA current source. When a capacitor is connected from OSC IN to ground (to select an alternative watchdog timeout period), the current source charges and discharges the timing capacitor to create the oscillator that controls the reset and watchdog timeout period. To prevent timing errors, minimize external current leakage sources at this pin, and locate the capacitor as close to OSCIN as possible. The sum of any PC board leakage plus the OSC capacitor leakage must be small compared to +100nA. Negative-Going VCC Transients While asserting resets to the P during power-up, power-down, and brownout conditions, these supervisors are relatively immune to shortduration negative-going VCC transients. It is usually undesirable to reset the P when VCC experiences only small glitches. Refer to Figure 29 for a graph of the maximum transient duration vs. the reset-comparator overdrive for which reset pulses are not generated. The graph was produced using negative-going pulses, starting at 5V and ending below the reset threshold by the magnitude indicated (reset comparator overdrive). The graph shows the maximum pulse width a negative-going VCC transient may typically have without causing a reset pulse to be issued. Date: 5/25/04 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over (c) Copyright 2004 Sipex Corporation 18 Watchdog Software Considerations A way to help the watchdog timer keep a closer watch on software execution involves setting and resetting the watchdog input at different points in the program, rather than "pulsing" the watchdog input high-low-high or low-high-low. This technique avoids a "stuck" loop where the watchdog timer continues to be reset within the loop, keeping the watchdog from timing out. Figure 30 shows an example flow diagram where the I/O driving the watchdog input is set high at the beginning of the program, set low at the beginning of every subrouting or loop, then set high again when the program returns to the beginning. If the program should "hang" in any subroutine, the I/O is continually set low and the watchdog timer is allowed to time out, causing a reset or interrupt to be issued. Maximum VCC Fall Time The VCC fall time is limited by the propagation delay of the battery switchover comparator and should not exceed 0.03V/s. A standard rule of thumb for filter capacitance on most regulators is on the order of 100F per amp of current. When the power supply is shut off or the main battery is disconnected, the associated initial VCC fall rate is just the inverse of 1A/100F = 0.01V/s. The VCC fall rate decreases with time as VCC falls exponentially, which more than satisfies the maximum fall-time requirement. START SET WDI LOW SUBROUTINE OR PROGRAM LOOP SET WDI HIGH RETURN END Figure 30. Watchdog Flow Diagram Date: 5/25/04 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over (c) Copyright 2004 Sipex Corporation 19 PACKAGE: 16 PIN NSOIC D e E/2 E1 E E1/2 SEE VIEW C 1 INDEX AREA (D/2 X E1/2) B b TOP VIEW WITH PLATING O1 b Gauge Plane L2 Seating Plane O1 L L1 O c VIEW C BASE METAL CONTACT AREA DIMENSIONS Minimum/Maximum (mm) 16 Pin NSOIC (JEDEC MS-012, AC - VARIATION) COMMON HEIGHT DIMENSION A A2 A1 SIDE VIEW SYMBOL A A1 A2 b c D E E1 e L L1 L2 O O1 MIN NOM MAX - 1.75 1.35 0.25 0.10 1.25 1.65 0.31 0.51 0.17 0.25 9.90 BSC 6.00 BSC 3.90 BSC 1.27 BSC 0.40 1.27 1.04 REF 0.25 BSC 0 8 5 - 15 16 PIN NSOIC Date: 5/25/04 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over (c) Copyright 2004 Sipex Corporation 20 PACKAGE: 16 PIN WSOIC D B E/2 E1 E E1/2 SEE VIEW C 1 INDEX AREA (D/2 X E1/2) 2 3 b e O1 TOP VIEW WITH PLATING b Gauge Plane L2 Seating Plane O1 L L1 O c VIEW C BASE METAL CONTACT AREA DIMENSIONS Minimum/Maximum (mm) 16 Pin SOIC (WIDE) (JEDEC MS-013, AA - VARIATION) COMMON HEIGHT DIMENSION A A2 A1 SIDE VIEW SYMBOL A A1 A2 b c D E E1 e L L1 L2 O O1 MIN NOM MAX 2.65 2.35 0.30 0.10 2.05 2.55 0.31 0.51 0.20 0.33 10.30 BSC 10.30 BSC 7.50 BSC 1.27 BSC 0.40 1.27 1.40 REF 0.25 BSC 0 8 5 15 16 PIN SOIC WIDE Date: 5/25/04 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over (c) Copyright 2004 Sipex Corporation 21 PACKAGE: 16 PIN PDIP A1 D A N D1 b3 e b1 b L A2 INDEX AREA E1 E 123 Dimensions in (mm) 16 PIN PDIP JEDEC MS-001 (BB) Variation MIN NOM MAX .015 .115 .014 .045 .030 .008 .735 .005 .300 .240 .130 .018 .060 .039 .010 .755 .310 .250 .100 BSC .300 BSC .115 .130 .430 .150 .210 .195 .022 .070 .045 .014 .775 .325 .280 E A A1 A2 b b2 b3 c D D1 E E1 e eA eB L SEE LEAD DETAIL c eA eB b C 16 pin PDIP Date: 5/25/04 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over (c) Copyright 2004 Sipex Corporation 22 ORDERING INFORMATION Part Number Temperature Range Package Type SP691ACP ............................................... 0OC to +70OC ............................................ 16-Pin PDIP SP691ACN ............................................... 0OC to +70OC ......................................... 16-Pin NSOIC SP691ACN/TR ......................................... 0OC to +70OC ......................................... 16-Pin NSOIC SP691ACT ............................................... 0OC to +70OC ........................................ 16-Pin WSOIC SP691ACT/TR ......................................... 0OC to +70OC ........................................ 16-Pin WSOIC SP691AEP ............................................. -40OC to +85OC .......................................... 16-Pin PDIP SP691AEN ............................................. -40OC to +85OC ....................................... 16-Pin NSOIC SP691AEN/TR ....................................... -40OC to +85OC ....................................... 16-Pin NSOIC SP691AET ............................................. -40OC to +85OC ...................................... 16-Pin WSOIC SP691AET/TR ........................................ -40OC to +85OC ...................................... 16-Pin WSOIC SP693ACP ............................................... 0OC to +70OC ............................................ 16-Pin PDIP SP693ACN ............................................... 0OC to +70OC ......................................... 16-Pin NSOIC SP693ACN/TR ......................................... 0OC to +70OC ......................................... 16-Pin NSOIC SP693ACT ............................................... 0OC to +70OC ........................................ 16-Pin WSOIC SP693ACT/TR ......................................... 0OC to +70OC ........................................ 16-Pin WSOIC SP693AEP ............................................. -40OC to +85OC .......................................... 16-Pin PDIP SP693AEN ............................................. -40OC to +85OC ....................................... 16-Pin NSOIC SP693AEN/TR ....................................... -40OC to +85OC ....................................... 16-Pin NSOIC SP693AET ............................................. -40OC to +85OC ...................................... 16-Pin WSOIC SP693AET/TR ........................................ -40OC to +85OC ...................................... 16-Pin WSOIC Available in lead free packaging. To order add "-L" suffix to part number. Example: SP691AEN/TR = standard; SP691AEN-L/TR = lead free /TR = Tape and Reel Pack quantity is 2500 for NSOIC and WSOIC. Corporation ANALOG EXCELLENCE Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Date: 5/25/04 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over (c) Copyright 2004 Sipex Corporation 23 ORDERING INFORMATION Part Number Temperature Range Package Type SP800LCP ............................................... 0OC to +70OC ............................................ 16-Pin PDIP SP800LCN ............................................... 0OC to +70OC ......................................... 16-Pin NSOIC SP800LCN/TR ......................................... 0OC to +70OC ......................................... 16-Pin NSOIC SP800LCT ................................................ 0OC to +70OC ........................................ 16-Pin WSOIC SP800LCT/TR .......................................... 0OC to +70OC ........................................ 16-Pin WSOIC SP800LEP ............................................. -40OC to +85OC .......................................... 16-Pin PDIP SP800LEN ............................................. -40OC to +85OC ....................................... 16-Pin NSOIC SP800LEN/TR ....................................... -40OC to +85OC ....................................... 16-Pin NSOIC SP800LET .............................................. -40OC to +85OC ...................................... 16-Pin WSOIC SP800LET/TR ........................................ -40OC to +85OC ...................................... 16-Pin WSOIC SP800MCP .............................................. 0OC to +70OC ............................................ 16-Pin PDIP SP800MCN .............................................. 0OC to +70OC ......................................... 16-Pin NSOIC SP800MCN/TR ........................................ 0OC to +70OC ......................................... 16-Pin NSOIC SP800MCT ............................................... 0OC to +70OC ........................................ 16-Pin WSOIC SP800MCT/TR ......................................... 0OC to +70OC ........................................ 16-Pin WSOIC SP800MEP ............................................. -40OC to +85OC .......................................... 16-Pin PDIP SP800MEN ............................................ -40OC to +85OC ....................................... 16-Pin NSOIC SP800MEN/TR ....................................... -40OC to +85OC ....................................... 16-Pin NSOIC SP800MET ............................................. -40OC to +85OC ...................................... 16-Pin WSOIC SP800MET/TR ....................................... -40OC to +85OC ...................................... 16-Pin WSOIC Available in lead free packaging. To order add "-L" suffix to part number. Example: SP800MEN/TR = standard; SP800MEN-L/TR = lead free /TR = Tape and Reel Pack quantity is 2500 for NSOIC and WSOIC. Corporation ANALOG EXCELLENCE Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Date: 5/25/04 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over (c) Copyright 2004 Sipex Corporation 24 |
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